1. Field of the Invention
The present invention relates to a semiconductor device and method of manufacturing the same, and in particular to a semiconductor device and method of manufacturing the same wherein it is possible to inhibit increases in interwiring capacitance in a highly integrated semiconductor device.
2. Description of the Related Art
Advances in semiconductor devices whereby the wiring has become progressively finer have created problems of increased interwiring capacitance. This results in reduced performance of the semiconductor device. Smaller intervals between wiring in the same wiring layer means that lowering the permittivity of the insulating film which is formed between the wiring fails to inhibit increased interwiring capacitance there.
With a view to inhibiting such increases in interwiring capacitance, Japanese Patent publication H7[1995]-114236 proposes a technique whereby air gaps are formed between the wiring in order to improve insulation properties. More specifically, as FIG. 6(a) shows, wiring 16 is formed on a semiconductor substrate 14 with the aid of an insulating film 15. Then, as may be seen from FIG. 6(b), the sputtering method is employed to embed an insulating film 18 between the wiring 16. Simultaneously, air gaps 17 are formed to correspond to the aspect ratio of the embedded section (ratio of the interval between the wiring 16 and its height).
However, the formation of air gaps 17 by the sputtering method and otherwise in the above mentioned conventional example is fraught with problems. That is to say, the insulating film which is formed on the side walls of the wiring 16 is less dense than that which is formed on other parts. This is because with the sputtering method there is directionality in the movement of particles as they are deposited on the substrate, and they are not easily deposited on the side walls of the wiring 16. This leads to problems of reliability, and of reduced ability to withstand voltage in particular. What is more, mask slipping means that the via (or through-hole) which serves to connect layers in the wiring 16 is not formed in its correct position, and this can cause shorting to occur between the wiring 16.
There follows, with reference to FIG. 7, a detailed explanation of the disadvantages of forming an insulating film 18 containing air gaps between the wiring 16 as described in relation to the conventional technology.
As FIG. 7(a) shows, in the conventional technology the sputtering method or bias CVD method are used to form an insulating film 18 containing air gaps 17 between the wiring 16, after which CMP (chemical mechanical polishing or a similar method is employed to flatten it. There is an inherent problem in that if the distance between adjacent wiring 16 is only a few mm or less, the insulating film formed on the respective side walls of adjacent wiring 16 will be less dense than that which is formed in places where the distance between the wiring 16 is measured in the tens of mm or above.
As may be seen from FIG. 7(b), a lithography process is used to form a via 20 which serves to perform the upper-layer wiring and interlayer connection. Here, it is impossible to ensure a satisfactory degree of accuracy in mask matching when using lithography techniques to form the lower-layer wiring 16 and the via 20. This leads to problems of shorting when the via 20 is not formed in the correct position on the wiring 16.
Where, as FIG. 7(c) shows, the CVD method is employed to form the via 20 and tungsten or other metals (compounds) are embedded, CVD gas (e.g. WF.sub.6) finds its way into a low-density insulating film 19 formed on the inner walls of the air gaps and the side walls of the wiring, resulting in the formation of inadequate insulating films 19a, 19b. These inadequate insulating films 19a, 19b are the cause of shorting. In addition to this, etching fluid and various types of gas (air etc.) find their way into the air gaps during formation of the via. This results in a lowering of the density during embedding of the via by the CVD method, and is problematic because it leads to the creation of cavities 21 in the via as well as inadequate connection.